• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for adjusting digital convergence is provided to use a data RAM as a buffer without accessing to an electrically erasable programmable read only memory(EEPROM) during adjusting digital convergence. CONSTITUTION: A method for adjusting digital convergence includes following steps. The data stored in a data save region of an electrically erasable programmable read only memory(EEPROM) in a micro computer is read. The data read is stored in a data read only memory(RAM) of a controller chip. Adjusting data for convergence is stored in a buffer region of the EEPROM and saved on the data save region. The data stored n the data RAM is read during convergence adjustment and convergence adjusting is performed. The data is temporarily stored in the data RAM and the data stored temporarily is stored in the EEPROM when the convergence adjusting is completed.
    公开号:KR20000065688A
    申请号:KR1019990012288
    申请日:1999-04-08
    公开日:2000-11-15
    发明作者:심재승
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Digital convergence control method
    The present invention relates to a digital convergence adjusting method of a digital image reproducing apparatus, and improves the adjusting speed by using a data RAM of a controller chip as a buffer area.
    The digital convergence adjustment circuit diagram of the digital video reproducing apparatus is shown in FIG. 1 as shown in FIG. 1, an ASIC controller chip 10 having a built-in data ROM 11, and a microcomputer 20 for executing a program for adjusting convergence according to key input. And an E 2 P ROM 31 comprising a buffer area 32 in which the convergence adjustment data is stored and a data save area 31 in which the adjusted data is stored.
    The microcomputer 20 stores the data stored in the data save area 31 of the E 2 P ROM 30 in the digital convergence data adjusting mode (the initial value setting data is set at the beginning of the set production, and the preset data thereafter). Is read and transmitted to the data RAM 11 of the controller chip 10 so that the convergence data is reflected.
    The adjustment data according to the convergence adjustment by the data stored in the data RAM 11 of the controller chip 10 is stored in the buffer area 32 of the E 2 P ROM 30. When the convergence adjustment is completed, the buffer is stored. The data stored in the area 32 is rewritten in the data save area 31 to complete the convergence adjustment.
    In other words, the data stored in the buffer 32 is recorded in the data save area 31 when the adjustment is completed.
    This will be described by the flowchart of FIG. 2.
    The microcomputer 20 is cone after recording the data RAM 11 of the controller chip 10 reads out the data stored in the E 2 P-ROM E 2 data saving area 31 of the P-ROM 30 checks the 30 Check if there is a version adjustment key input.
    If there is an adjustment key input, it recognizes the adjustment key and checks whether it is the end code if it is the correct code. If it is not the end code, data processing is performed to adjust the convergence. The convergence adjustment data at this time is stored in the E 2 P ROM 30. It is stored in the buffer area 32.
    In this way, if the input of the adjustment key is correctly input, data is written into the data RAM 11, data processing is performed, and then stored in the buffer area 32. The stored data is transferred to the data save area 31 and recorded.
    In this conventional method, since the data RAM 11 of the control chip 10 cannot be read from the outside, that is, data exchange between the microcomputer 20 and the controller chip 10 is performed unilaterally. In addition, there is a problem in the processing speed decrease due to frequent access (E 2 P ROM 30).
    According to the present invention, the data ram of a controller chip performing digital convergence can be read / written from a microcomputer, thereby increasing the data adjusting speed by directly accessing the data ram without the need of a buffer area required for the conventional E 2 P ROM. It can be verified to ensure data reliability.
    In the method of adjusting the convergence of a digital image reproducing apparatus, the present invention uses a data RAM of a controller chip that controls on-screen convergence as a buffer area of the microcomputer, and uses the E 2 P ROM only as a data recording area. In this case, the data RAM of the present invention is configured to be read / write in a microcomputer.
    1 is a conventional digital convergence adjustment circuit diagram
    2 is a flow chart of an existing digital convergence adjustment.
    3 is a digital convergence adjustment circuit diagram of the present invention.
    4 is a digital convergence adjustment flowchart of the present invention.
    [Explanation of symbols on the main parts of the drawings]
    10,40: controller chip 11,41: data RAM
    20,50: Micom 30,60: E 2 P Rom
    31,61: data save area 32: buffer area
    As shown in FIG. 3, the controller chip 40 in which the data ROM 41 is embedded, the microcomputer 50 for executing the convergence adjustment program according to key input, and the data whose convergence has been adjusted are stored. It consists of an E 2 P ROM 60 consisting only of the data save area 61 to be stored.
    Here, the data RAM 41 of the controller chip 40 is designed to be read / write from the microcomputer 50, and the microcomputer 50 is a buffer region of the E 2 PROM 30 in the existing convergence adjusting program. Unlike the method of using 32), the data RAM 41 of the controller chip 40 is used as a temporary storage place of the convergence adjustment data.
    According to the present invention, in the digital convergence adjustment mode, the microcomputer 50 reads the data stored in the data save area 61 of the E 2 P ROM 60 and stores the data stored in the data RAM 41 of the controller chip 40. After recording, the data stored in the data RAM 41 is checked and convergence adjustment is performed, and the converged adjusted data is recorded in the data RAM 41 again.
    That is, the data RAM 41 of the controller chip 40 is used as a temporary storage place of the adjustment data at the time of convergence adjustment.
    This will be described in detail based on the flowchart of FIG. 4.
    The microcomputer 50 is E 2 recorded in the P-ROM data RAM 41 of the controller chip 40 reads out the data stored in the data saving area 61 of E 2 P-ROM 60 is checked (60) and cones Check if there is a version adjustment key input.
    When the convergence adjustment key is input, it enters the convergence adjustment mode and checks whether data is stored in the data RAM 41.
    In other words, the data RAM 41 of the controller chip 40 should store data recorded in the data save area 61 of the E 2 P ROM 60 in the convergence adjustment mode.
    Check the convergence adjustment key to confirm that the correct code is entered when the adjustment key input is recognized. If the correct code is confirmed, check the end code authorization.
    If the convergence adjustment key is input instead of the end code, data processing is performed to perform the convergence adjustment, and the convergence adjustment data is stored in the data RAM 41.
    The above process is repeated to perform overall convergence adjustment. When the convergence adjustment is completed and the end code is input, the data stored in the data RAM 41 where the adjustment data up to this point are recorded is stored in the E 2 P ROM (60). Is written into the data sable area 61, and the convergence adjustment mode is terminated.
    According to the present invention, the data recorded in the E 2 P ROM 60 is initially read and then recorded in the E 2 P ROM 60 only in the final data save mode, and the adjustment data in the convergence adjustment mode is E. By temporarily storing data in the data RAM 41 instead of the 2 P ROM 60, the access speed of the E 2 P ROM 60 can be reduced, thereby improving the data processing speed and the size of the E 2 P ROM 60 can be reduced. have.
    The present invention uses the data RAM as a buffer without accessing the E 2 P ROM in digital convergence adjustment, so that the speed can be improved and the data RAM can be checked, thereby improving the reliability of the data.
    In addition, the E 2 PROM requires only a data save area and no buffer area, thereby reducing the size of the E 2 P ROM, thereby reducing cost.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] The microcomputer reads the data stored in the data save area of the E 2 P ROM and stores it in the data RAM of the controller chip. When adjusting the convergence, the adjustment data is stored in the buffer area of the E 2 P ROM and stored in the data save area. In the version adjustment method,
    When adjusting the convergence, read the data stored in the data RAM, adjust the convergence, and temporarily store the adjusted adjusted data in the data RAM. Then, when the convergence adjustment is completed, the data stored in the data RAM is stored in the E 2 P ROM. Digital convergence adjustment method characterized in that the stored.
    [2" claim-type="Currently amended] The method of claim 1, wherein the data RAM of the controller chip is designed to be read and write.
    [3" claim-type="Currently amended] 2. The method of claim 1, wherein the E 2 PROM consists only of a data save region.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-04-08|Application filed by 윤종용, 삼성전자 주식회사
    1999-04-08|Priority to KR1019990012288A
    2000-11-15|Publication of KR20000065688A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019990012288A|KR20000065688A|1999-04-08|1999-04-08|Digital convergence control method|
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